Discreet logic schematics for a U.A.R.T and M.O.D.E

[Don Yuniskis]

In article <1995Oct3...@omega.ntu.ac.sg>,
PAUL WU -CHRISTMAS IS COMING, *HIAO GUY* <bh72...@omega.ntu.ac.sg> wrote:
>In article <473oni$i...@turkey.tdh.texas.gov>, gleb...@glo.state.tx.us (Gregory Leblanc) writes:
>> Hello, I'm looking for information on the above subject. I'm would like just
>> the public domain or industry standard information or a source to purchase it
>> from. If possible something not to far out of date. To better understand
>> the devices I 'm trying to build them from transistors and logic gates only.
>> no M.S.I or L.S.I is to be used. I've been looking for a while and this is a
>> last ditch effort for help.

Well, I think most edge triggered FF's are considered MSI... I guess
you could try building a M-S version out of gates but that's being a bit
silly, don't you think?

> Anyway, u could "re-design" it from the state diagrams and timing
>chart of the chips.

Yes, this is the approach I used for a class assignment some years ago.
It's really pretty simple -- the toughest part is building the DPLL
(assuming you want to be that clever!)

Grab a databook on one of the *older* UARt chips (6402?) so you
don't get sidetracked by baudrate generator, modem control signals,
etc. The basics of the serializer/deserializer are pretty straight
forward. And OE, PE, FE are almost trivial to implement once you
understand *exactly* what they signal...

G'luck!